Semiconductor devices

ABSTRACT

A semiconductor device includes a counter control signal generation circuit and an access information generation circuit. The counter control signal generation circuit generates a count enablement signal, a reset signal and a count increment signal in response to a first row address selected as a target address and a second row address selected as a neighboring address. The access information generation circuit receives the count enablement signal, the reset signal and the count increment signal to generate a first access information signal including information on the number of times that the target address is selected and a second access information signal including information on the number of times that the neighboring address is selected.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C 119(a) to KoreanPatent Application No. 10-2016-0175756, filed on Dec. 21, 2016, which isherein incorporated by references in its entirety.

BACKGROUND 1. Technical Field

Embodiments of the present disclosure relate to semiconductor devicesexecuting a refresh operation.

2. Related Art

A semiconductor device such as a dynamic random access memory (DRAM)device includes a plurality of memory cells for storing data. Each ofDRAM cells is configured to include a cell capacitor and a celltransistor. The DRAM device stores data therein by discharging orcharging the cell capacitors. Once the cell capacitor is charged ordischarged to store a datum therein, an amount of electric charge storedin the cell capacitor is ideally constant over time. However, the amountof electric charge stored in the cell capacitor actually varies becauseof a voltage difference between the cell capacitor and a circuitadjacent to the cell capacitor or because of a leakage current of thecell capacitor. In particular, if the amount of electric charge storedin the cell capacitor is reduced, the cell capacitor may lose a datumstored therein, resulting in a malfunction of the DRAM device. Thus, theDRAM device may require a refresh operation to prevent the memory cellsfrom losing their data.

As a semiconductor device becomes more highly integrated with thedevelopment of process technologies, a distance between memory cells aswell as a distance between word lines connected to the memory cells hasbeen continuously reduced. If the distance between the word lines isreduced, data stored in memory cells adjacent to a selected memory cellmay be changed due to a coupling phenomenon or an interferencephenomenon between the word lines.

SUMMARY

Recently, an additional refresh scheme has been applied to a word lineadjacent to a target word line, which is frequently accessed oractivated, in order to prevent memory cells connected to the adjacentword line from losing their data due to the interference phenomenonbetween the word lines. The additional refresh scheme applied to theadjacent word line is referred to as ‘smart refresh.’

Various embodiments are directed to semiconductor devices counting upthe number of times that word lines are selected to perform a smartrefresh operation.

According to an embodiment, a semiconductor device includes a countercontrol signal generation circuit and an access information generationcircuit. The counter control signal generation circuit generates a countenablement signal, a reset signal and a count increment signal inresponse to a first row address selected as a target address and asecond row address selected as a neighboring address. The accessinformation generation circuit receives the count enablement signal, thereset signal and the count increment signal to generate a first accessinformation signal including information on the number of times that thetarget address is selected and a second access information signalincluding information on the number of times that the neighboringaddress is selected.

According to another embodiment, a semiconductor device includes acontrol signal generation circuit, an information storage circuit and acounter. The control signal generation circuit generates a first outputcontrol signal, a first input control signal and a reset signal inresponse to a first row address selected as a target address during afirst period. In addition, the control signal generation circuitgenerates a second output control signal, a second input control signaland a count increment signal in response to a second row addressselected as a neighboring address during a second period. Theinformation storage circuit outputs or stores a first access informationsignal including information on the number of times that the targetaddress is selected and a second access information signal includinginformation on the number of times that the neighboring address isselected, in response to the first output control signal, the firstinput control signal, the second output control signal and the secondinput control signal. The counter resets or counts the first accessinformation signal and the second access information signal in responseto the reset signal and the count increment signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the present disclosure will become more apparentin view of the attached drawings and accompanying detailed description,in which:

FIG. 1 is a block diagram illustrating a semiconductor device accordingto an embodiment of the present disclosure;

FIG. 2 is a table illustrating a target address and neighboringaddresses, which are set in the semiconductor device of FIG. 1;

FIG. 3 is a block diagram illustrating an access information generationcircuit included in the semiconductor device of FIG. 1 according to anembodiment of the present disclosure;

FIG. 4 is a timing diagram illustrating an operation of thesemiconductor device illustrated in FIGS. 1, 2, and 3;

FIG. 5 is a block diagram illustrating a semiconductor device accordingto another embodiment of the present disclosure;

FIG. 6 is a block diagram illustrating an information storage circuitincluded in the semiconductor device of FIG. 5 according to anembodiment of the present disclosure;

FIG. 7 is a timing diagram illustrating an operation of thesemiconductor device illustrated in FIGS. 5 and 6; and

FIG. 8 is a block diagram illustrating an electronic system including atleast one of the semiconductor devices illustrated in FIGS. 1 and 5according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present disclosure will be describedhereinafter with reference to the accompanying drawings. However, theembodiments described herein are for illustrative purposes only and arenot intended to limit the scope of the present disclosure.

FIG. 1 is a block diagram illustrating a semiconductor device accordingto an embodiment of the present disclosure. The semiconductor device mayinclude a target address generation circuit 11, a period signalgeneration circuit 12, a neighboring address generation circuit 13, acounter control signal generation circuit 14, an access informationgeneration circuit 15, and a refresh control circuit 16.

The target address generation circuit 11 may generate a target addressTADD, which is based on data of address bits included in acommand/address signal CA<1:M>, in response to a period signal PDS, Mbeing a positive integer. The target address generation circuit 11 maydecode the data of the address bits included in the command/addresssignal CA<1:M> and generate the target address TADD during a period whena predetermined internal operation is performed, in response to theperiod signal PDS. The command/address signal CA<1:M> may include atleast one of a command and an address signal. The number “M” of bitsincluded in the command/address signal CA<1:M> may be set at differentvalues according to different embodiments. The target address TADD maybe generated by decoding the data of the address bits included in thecommand/address signal CA<1:M>, and may be set to correspond to a rowaddress, which is enabled. The row address may be enabled to activateany one of word lines. The enabled row address may change according to alogic level combination of the data of the address bits included in thecommand/address signal CA<1:M>.

The period signal generation circuit 12 may generate the period signalPDS, which is enabled during a predetermined period, based on thecommand/address signal CA<1:M>. The period signal generation circuit 12may decode data of command bits included in the command/address signalCA<1:M> and generate the period signal PDS, which is enabled during theperiod when the predetermined internal operation is performed. Forexample, the period signal generation circuit 12 may decode data of thecommand bits included in the command/address signal CA<1:M> and generatethe period signal PDS, which is enabled during a period when an activeoperation is performed. The period signal PDS may be enabled during aperiod when at least one of various internal operations, such as a readoperation, a write operation, a refresh operation, and a standbyoperation, is performed according to an embodiment.

In an embodiment, the command of the command/address signal CA<1:M> mayinclude data of the command bits, and the address signal of thecommand/address signal CA<1:M> may include data of the address bits. Mcorresponds to a sum of the number of command bits and the number ofaddress bits.

The neighboring address generation circuit 13 may generate first toJ^(th) neighboring addresses NADD<1:J> based on the target address TADD,in response to the period signal PDS, J being a positive integer. Theneighboring address generation circuit 13 may select row addressesneighboring with the row address corresponding to the target addressTADD as the first to J^(th) neighboring addresses NADD<1:J> during theperiod when the predetermined internal operation is performed, inresponse to the period signal PDS. The number “J” of bits included inthe first to J^(th) neighboring addresses NADD<1:J> may change accordingto embodiments. An operation in which the target address TADD and thefirst to J^(th) neighboring addresses NADD<1:J> are selected will bedescribed in detail with reference to FIG. 2.

The counter control signal generation circuit 14 may generate first toL^(th) count enablement signals CNTEN<1:L>, first to L^(th) resetsignals RST<1:L>, and a count increment signal CNT_INC based on thetarget address TADD and the first to J^(th) neighboring addressesNADD<1:J>, in response to the period signal PDS, L being a positiveinteger. The counter control signal generation circuit 14 may generatethe first to L^(th) reset signals RST<1:L>, which are selectivelyenabled in order to reset counters (not shown). The counters may countthe number of times that the row address corresponding to the targetaddress TADD is selected during a period when a predetermined internaloperation is performed, in response to the period signal PDS.

The counter control signal generation circuit 14 may generate the firstto L^(th) count enablement signals CNTEN<1:L>, which are selectivelyenabled in order to activate the counters (not shown), the counterscounting up the number of times that row addresses corresponding to thefirst to J^(th) neighboring addresses NADD<1:J> are selected during aperiod when a predetermined internal operation is performed, in responseto the period signal PDS. The counter control signal generation circuit14 may generate a count increment signal CNT_INC, which is enabled whenthe target address TADD is selected during the period when thepredetermined internal operation is performed, in response to the periodsignal PDS.

The access information generation circuit 15 may generate first toL^(th) access information signals AIF(1)<1:K>˜AIF(L)<1:K> based on thefirst to L^(th) count enablement signals CNTEN<1:L>, the first to L^(th)reset signals RST<1:L>, and the count increment signal CNT_INC, K beinga positive integer. The access information generation circuit 15 mayselectively count when one of the first to L^(th) access informationsignals AIF(1)<1:K>˜AIF(L)<1:K> corresponds to any one of the first toL^(th) count enablement signals CNTEN<1:L> that is enabled, and outputthe selected access information signal that has a value incremented byone each time the circuit 15 counts. The access information generationcircuit 15 may selectively count in response to the count incrementsignal CNT_INC.

For example, if the N^(th) count enablement signal CNTEN<N> and thecount increment signal CNT_INC are enabled when the N^(th) accessinformation signal AIF(N)<1:3> has a logic level combination of ‘010,’the N^(th) access information signal AIF(N)<1:3> may be counted up by anincrement of one, e.g., ‘001,’ to have a logic level combination of‘011.’ In the N^(th) access information signal AIF(N)<1:3>, the logiclevel combination of ‘011’ means that second and third bits AIF(N)<2:3>of the N^(th) access information signal AIF(N)<1:3> have a logic“high(1)” level and a first bit AIF(N)<1> of the N^(th) accessinformation signal AIF(N)<1:3> has a logic “low(0)” level. Aconfiguration of the access information generation circuit 15 will bedescribed in detail with reference to FIG. 3.

The refresh control circuit 16 may perform a refresh operation inresponse to the first to L^(th) access information signalsAIF(1)<1:K>˜AIF(L)<1:K>. The refresh control circuit 16 may perform arefresh operation for memory cells (not shown) selected by a row addresscorresponding to a specific one of the first to L^(th) accessinformation signals AIF(1)<1:K>˜AIF(L)<1:K>, when the specific accessinformation signal is counted by more than a predetermined number oftimes (or maximum counter value).

FIG. 2 is a table illustrating a target address and neighboringaddresses, which are set in the semiconductor device of FIG. 1.Referring to FIG. 2, an operation in which the target address TADD andthe first to J^(th) neighboring addresses NADD<1:J> are selected fromfirst to L^(th) row addresses RADD<1:L> may be determined according tothe number “J” of bits included in the first to J^(th) neighboringaddresses NADD<1:J>. The first to L^(th) row addresses RADD<1:L> may begenerated by decoding the data of the address bits of thecommand/address signal CA<1:M>, and may include bits, one of which isselectively enabled. If the N^(th) row address RADD<N> is selected asthe target address TADD when the number “J” of bits included in thefirst to J^(th) neighboring addresses NADD<1:J> is two, the (N−1)^(th)row address RADD<N−1> may be selected as the first neighboring addressNADD<1> and the (N+1)^(th) row address RADD<N+1> may be selected as thesecond neighboring address NADD<2>. If the N^(th) row address RADD<N> isselected as the target address TADD when the number “J” of bits includedin the first to J^(th) neighboring addresses NADD<1:J> is four, the(N−2)^(th) row address RADD<N−2>, the (N−1)^(th) row address RADD<N−1>,the (N+1)^(th) row address RADD<N+1>, and the (N+2)^(th) row addressRADD<N+2> may be selected as the first to fourth neighboring addressesNADD<1:4>, respectively.

FIG. 3 is a block diagram illustrating the access information generationcircuit 15 included in the semiconductor device of FIG. 1 according toan embodiment of the present disclosure. The access informationgeneration circuit 15 may include first to L^(th) counters 15(1)˜15(L).

The first counter 15(1) may generate the first access information signalAIF(1)<1:K> based on the first count enablement signal CNTEN<1>, thefirst reset signal RST<1>, and the count increment signal CNT_INC. Thefirst counter 15(1) may output the first access information signalAIF(1)<1:K>, which is counted when the first count enablement signalCNTEN<1> and the count increment signal CNT_INC are enabled. The firstaccess information signal AIF(1)<1:K> may be counted by increasing avalue of the first access information signal AIF(1)<1:K> by an incrementof one. The first counter 15(1) may initialize the first accessinformation signal AIF(1)<1:K>, so that the first access informationsignal AIF(1)<1:K> has an initial value, if the first reset signalRST<1> is enabled. The first access information signal AIF(1)<1:K> maybe initialized so that all of bits included in the first accessinformation signal AIF(1)<1:K> have a logic “low” level. The initialvalue of the first access information signal AIF(1)<1:K> may be set atdifferent values according to different embodiments.

The second counter 15(2) may generate the second access informationsignal AIF(2)<1:K> based on the second count enablement signal CNTEN<2>,the second reset signal RST<2>, and the count increment signal CNT_INC.The second counter 15(2) may output the second access information signalAIF(2)<1:K> that is counted when the second count enablement signalCNTEN<2> and the count increment signal CNT_INC are enabled. The secondaccess information signal AIF(2)<1:K> may be counted by increasing avalue of the second access information signal AIF(2)<1:K> by anincrement of one. The second counter 15(2) may initialize the secondaccess information signal AIF(2)<1:K>, such that the second accessinformation signal AIF(2)<1:K> has an initial value, if the second resetsignal RST<2> is enabled. The second access information signalAIF(2)<1:K> may be initialized so that all of bits included in thesecond access information signal AIF(2)<1:K> have a logic “low” level.The initial value of the second access information signal AIF(2)<1:K>may be set at different values according to different embodiments.

The (N−1)^(th) counter 15(N−1) may generate the (N−1)^(th) accessinformation signal AIF(N−1)<1:K> based on the (N−1)^(th) countenablement signal CNTEN<N−1>, the (N−1)^(th) reset signal RST<N−1>, andthe count increment signal CNT_INC. The (N−1)^(th) counter 15(N−1) mayoutput the (N−1)^(th) access information signal AIF(N−1)<1:K> that iscounted when the (N−1)^(th) count enablement signal CNTEN<N−1> and thecount increment signal CNT_INC are enabled. The (N−1)^(th) accessinformation signal AIF(N−1)<1:K> may be counted by increasing a value ofthe (N−1)^(th) access information signal AIF(N−1)<1:K> by an incrementof one. The (N−1)^(th) counter 15(N−1) may initialize the (N−1)^(th)access information signal AIF(N−1)<1:K> so that the (N−1)^(th) accessinformation signal AIF(N−1)<1:K> has an initial value, if the (N−1)^(th)reset signal RST<N−1> is enabled. The (N−1)^(th) access informationsignal AIF(N−1)<1:K> may be initialized so that all of bits included inthe (N−1)^(th) access information signal AIF(N−1)<1:K> have a logic“low” level. The initial value of the (N−1)^(th) access informationsignal AIF(N−1)<1:K> may be set at different values according todifferent embodiments.

The N^(th) counter 15(N) may generate the N^(th) access informationsignal AIF(N)<1:K> based on the N^(th) count enablement signal CNTEN<N>,the N^(th) reset signal RST<N>, and the count increment signal CNT_INC.The N^(th) counter 15(N) may output the N^(th) access information signalAIF(N)<1:K> that is counted when the N^(th) count enablement signalCNTEN<N> and the count increment signal CNT_INC are enabled. The N^(th)access information signal AIF(N)<1:K> may be counted by increasing avalue of the N^(th) access information signal AIF(N)<1:K> by anincrement of one. The N^(th) counter 15(N) may initialize the N^(th)access information signal AIF(N)<1:K> so that the N^(th) accessinformation signal AIF(N)<1:K> has an initial value, if the N^(th) resetsignal RST<N> is enabled. The N^(th) access information signalAIF(N)<1:K> may be initialized such that all of bits included in theN^(th) access information signal AIF(N)<1:K> have a logic “low” level.The initial value of the N^(th) access information signal AIF(N)<1:K>may be set at different values according to different embodiments.

The (N+1)^(th) counter 15(N+1) may generate the (N+1)^(th) accessinformation signal AIF(N+1)<1:K> based on the (N+1)^(th) countenablement signal CNTEN<N+1>, the (N+1)^(th) reset signal RST<N+1>, andthe count increment signal CNT_INC. The (N+1)^(th) counter 15(N+1) mayoutput the (N+1)^(th) access information signal AIF(N+1)<1:K> that iscounted when the (N+1)^(th) count enablement signal CNTEN<N+1> and thecount increment signal CNT_INC are enabled. The (N+1)^(th) accessinformation signal AIF(N+1)<1:K> may be counted by increasing a value ofthe (N+1)^(th) access information signal AIF(N+1)<1:K> by an incrementof one. The (N+1)^(th) counter 15(N+1) may initialize the (N+1)^(th)access information signal AIF(N+1)<1:K> so that the (N+1)^(th) accessinformation signal AIF(N+1)<1:K> has an initial value, if the (N+1)^(th)reset signal RST<N+1> is enabled. The (N+1)^(th) access informationsignal AIF(N+1)<1:K> may be initialized so that all of bits included inthe (N+1)^(th) access information signal AIF(N+1)<1:K> have a logic“low” level. The initial value of the (N+1)^(th) access informationsignal AIF(N+1)<1:K> may be set at different values according todifferent embodiments.

The L^(th) counter 15(L) may generate the L^(th) access informationsignal AIF(L)<1:K> based on the L^(th) count enablement signal CNTEN<L>,the L^(th) reset signal RST<L>, and the count increment signal CNT_INC.The L^(th) counter 15(L) may output the L^(th) access information signalAIF(L)<1:K> that has been counted when the L^(th) count enablementsignal CNTEN<L> and the count increment signal CNT_INC are enabled. TheL^(th) access information signal AIF(L)<1:K> may be counted byincreasing a value of the L^(th) access information signal AIF(L)<1:K>by an increment of one. The L^(th) counter 15(L) may initialize theL^(th) access information signal AIF(L)<1:K> so that the L^(th) accessinformation signal AIF(L)<1:K> has an initial value, if the L^(th) resetsignal RST<L> is enabled. The L^(th) access information signalAIF(L)<1:K> may be initialized so that all of bits included in theL^(th) access information signal AIF(L)<1:K> have a logic “low” level.The initial value of the L^(th) access information signal AIF(L)<1:K>may be set at different values according to different embodiments.

An operation of the semiconductor device having the aforementionedconfiguration illustrated in FIGS. 1 and 3 will be described hereinafterin detail with reference to FIG. 4 in conjunction with an example inwhich the number “J” of bits included in the first to J^(th) neighboringaddresses NADD<1:J> is two.

During a period from a point of time “T11” till a point of time “T12,”the period signal PDS may be set to have a logic “high” level, and anactive operation may be performed. The target address TADD may beselected in synchronization with a point of time when the period signalPDS is enabled to have a logic “high” level, and the first and secondneighboring addresses NADD<1> and NADD<2> may be selected according tothe target address TADD. The target address TADD and the first andsecond neighboring addresses NADD<1> and NADD<2> may be selected andgenerated from the first to L^(th) row addresses RADD<1:L>, as describedabove with reference to FIG. 2. The first to L^(th) row addressesRADD<1:L> may include bits, one of which is selectively enabled bydecoding the address bits included in the command/address signalCA<1:M>.

In the present embodiment, the N^(th) row address RADD<N> may beselected as the target address TADD, and the (N−1)^(th) row addressRADD<N−1> and the (N+1)^(th) row address RADD<N+1> may be selected asthe first and second neighboring addresses NADD<1> and NADD<2>,respectively.

Therefore, the N^(th) reset signal RST<N> may be enabled to have a logic“high” level by the N^(th) row address RADD<N>, which is selected as thetarget address TADD. The N^(th) access information signal AIF(N)<1:K>including information on the number of times that the N^(th) row addressRADD<N> is selected as a neighboring address may be initialized to havean initial value in response to the N^(th) reset signal RST<N>, which isenabled. That is, the N^(th) row address RADD<N> is selected as thetarget address TADD, a value of the N^(th) access information signalAIF(N)<1:K> is reset to the initial value.

The (N−1)^(th) count enablement signal CNTEN<N−1> may be enabled to havea logic “high” level by the (N−1)^(th) row address RADD<N−1>, which isselected as the first neighboring address NADD<1>. The (N−1)^(th) accessinformation signal AIF(N−1)<1:K> including information on the number oftimes that the (N−1)^(th) row address RADD<N−1> is selected as aneighboring address may be counted in response to the (N−1)^(th) countenablement signal CNTEN<N−1> and the count increment signal CNT_INC,which are enabled. The (N−1)^(th) access information signalAIF(N−1)<1:K> may be counted by increasing a value of the (N−1)^(th)access information signal AIF(N−1)<1:K> by an increment of one. That is,the (N−1)^(th) row address RADD<N−1> is selected as a neighboringaddress, a value of the (N−1)^(th) access information signalAIF(N−1)<1:K> is incremented by one.

The (N+1)^(th) count enablement signal CNTEN<N+1> may be enabled to havea logic “high” level by the (N+1)^(th) row address RADD<N+1>, which isselected as the second neighboring address NADD<2>. The (N+1)^(th)access information signal AIF(N+1)<1:K> including information on thenumber of times that the (N+1)^(th) row address RADD<N+1> is selected asa neighboring address may be counted in response to the (N+1)^(th) countenablement signal CNTEN<N+1> and the count increment signal CNT_INC,which are enabled. The (N+1)^(th) access information signalAIF(N+1)<1:K> may be counted by increasing a value of the (N+1)^(th)access information signal AIF(N+1)<1:K> by an increment of one. That is,the (N+1)^(th) row address RADD<N+1> is selected as a neighboringaddress, a value of the (N+1)^(th) access information signalAIF(N+1)<1:K> is incremented by one.

As described above, a semiconductor device according to an embodimentmay reset an access information signal corresponding to a row addressthat is selected as a target address, and may count an accessinformation signal corresponding to a row address that is set as aneighboring address. Electric charge stored in memory cells connected toa neighboring word line selected by the row address set as theneighboring address may be lost due to interference between a targetword line selected by the row address selected as the target address andthe neighboring word line selected by the row address set as theneighboring address. Thus, a refresh operation may be performed torefresh memory cells connected to a word line when the word line isselected as a neighboring word line more than a predetermined number oftimes.

FIG. 5 is a block diagram illustrating a semiconductor device accordingto another embodiment of the present disclosure. The semiconductordevice may include a target address generation circuit 31, a periodsignal generation circuit 32, a neighboring address generation circuit33, a control signal generation circuit 34, an information storagecircuit 35, a counter 36, and a refresh control circuit 37.

The target address generation circuit 31 may generate a target addressTADD based on data of address bits included in a command/address signalCA<1:M>, in response to a first period signal PDS1. The target addressgeneration circuit 31 may decode the data of the address bits includedin the command/address signal CA<1:M> and generate the target addressTADD during a first period when the first period signal PDS1 is enabled.The first period may be set to be a period from a point of time when apredetermined internal operation starts until a point of time when apredetermined time elapses after the predetermined internal operationstarts.

The command/address signal CA<1:M> may include at least one of a commandand an address signal. The number “M” of bits included in thecommand/address signal CA<1:M> may be set at different values accordingto different embodiments. The target address TADD may be set tocorrespond to a row address, which is enabled by decoding the data ofthe address bits included in the command/address signal CA<1:M>. The rowaddress may be enabled to activate any one of word lines. The enabledrow address may change according to a logic level combination of thedata of the address bits included in the command/address signal CA<1:M>.

The period signal generation circuit 32 may generate the first periodsignal PDS1, a second period signal PDS2, and a third period signalPDS3, based on the command/address signal CA<1:M>. The period signalgeneration circuit 32 may decode command bits included in thecommand/address signal CA<1:M>, and generate the first period signalPDS1 that is enabled during the first period, the second period signalPDS2 that is enabled during a second period, and the third period signalPDS3 that is enabled during a third period. The first to third periodsmay be set by dividing a period when the predetermined internaloperation is performed.

For example, a period when an active operation is performed may bedivided into the first to third periods. The period signal generationcircuit 32 may decode the command bits included in the command/addresssignal CA<1:M> and generate the first to third period signals PDS1,PDS2, and PDS3, which are sequentially enabled during the period whenthe active operation is performed.

Therefore, the first to third period signals PDS1, PDS2, and PDS3 may begenerated to be sequentially enabled during a period when at least oneof various internal operations such as a read operation, a writeoperation, a refresh operation, and a standby operation is performed,according to embodiments.

The neighboring address generation circuit 33 may generate first toJ^(th) neighboring addresses NADD<1:J> based on the target address TADD,in response to the second and third period signals PDS2 and PDS3. Theneighboring address generation circuit 33 may select row addressesneighboring with a target row address corresponding to the targetaddress TADD as the first to J^(th) neighboring addresses NADD<1:J>during the second and third periods when the second and third periodsignals PDS2 and PDS3 are enabled.

If the number “J” of bits included in the first to J^(th) neighboringaddresses NADD<1:J> is two, a row address adjacent to the target rowaddress in a first direction may be selected as the first neighboringaddress NADD<1> during the second period, and a row address adjacent tothe target row address in a second direction may be selected as thesecond neighboring address NADD<2> during the third period. The seconddirection may be opposite to the first direction.

If the number “J” of bits included in the first to J^(th) neighboringaddresses NADD<1:J> is four, two row addresses adjacent to the targetrow address in the first direction may be selected as the first andsecond neighboring addresses NADD<1:2> during the second period, and tworow addresses adjacent to the target row address in the second directionmay be selected as the third and fourth neighboring addresses NADD<3:4>during the third period.

The control signal generation circuit 34 may generate first to L^(th)output control signals DOUT<1:L>, first to L^(th) input control signalsDIN<1:L>, and a reset signal RST based on the first period signal PDS1and the target address TADD. The control signal generation circuit 34may generate the first to L^(th) output control signals DOUT<1:L>, whichare enabled to output access information on the number of times that arow address corresponding to the target address TADD is selected duringthe first period when the first period signal PDS1 is enabled.

For example, if an N^(th) row address RADD<N> is selected as the targetaddress TADD, the N^(th) output control signal DOUT<N>, which is enabledduring the first period, may be generated. The N^(th) input controlsignal DIN<N> corresponding to the N^(th) row address RADD<N> may beenabled after the first period ends. The control signal generationcircuit 34 may generate the reset signal RST, which is enabled duringthe first period.

The control signal generation circuit 34 may generate the first toL^(th) output control signals DOUT<1:L>, the first to L^(th) inputcontrol signals DIN<1:L>, and a count increment signal CNT_INC based onthe second and third period signals PDS2 and PDS3 and the first toJ^(th) neighboring addresses NADD<1:J>. The control signal generationcircuit 34 may generate the first to L^(th) output control signalsDOUT<1:L>, which are enabled to output access information on the numberof times that row addresses corresponding to the first to J^(th)neighboring addresses NADD<1:J> are selected during the second and thirdperiods when the second and third period signals PDS2 and PDS3 areenabled.

If the N^(th) row address RADD<N> is selected as the target addressTADD, the control signal generation circuit 34 may generate the(N−1)^(th) output control signal DOUT<N−1>, which is enabled to outputaccess information on the number of times that the (N−1)^(th) rowaddress RADD<N−1> is selected as a neighboring address, during thesecond period. The (N−1)^(th) input control signal DIN<N−1>corresponding to the (N−1)^(th) row address RADD<N−1>, which is selectedas the first neighboring address NADD<1>, may be enabled after thesecond period ends.

If the N^(th) row address RADD<N> is selected as the target addressTADD, the control signal generation circuit 34 may generate the(N+1)^(th) output control signal DOUT<N+1>, which is enabled to outputaccess information on the number of times that the (N+1)^(th) rowaddress RADD<N+1> is selected as a neighboring address, during the thirdperiod. The (N+1)^(th) input control signal DIN<N+1> corresponding tothe (N+1)^(th) row address RADD<N+1>, which is selected as the secondneighboring address NADD<2>, may be enabled after the third period ends.The control signal generation circuit 34 may generate the countincrement signal CNT_INC, which is enabled during the second and thirdperiods.

The information storage circuit 35 may include a plurality of storagecircuits (not shown), which are capable of storing first to L^(th)access information signals AIF(1)<1: K>˜AIF(L)<1:K>. The informationstorage circuit 35 may output the first to L^(th) access informationsignals AIF(1)<1:K>˜AIF(L)<1:K> stored therein in response to the firstto L^(th) output control signals DOUT<1:L>. The information storagecircuit 35 may receive the first to L^(th) access information signalsAIF(1)<1:K>˜AIF(L)<1:K> from the counter 36 and store the first toL^(th) access information signals AIF(1)<1:K>˜AIF(L)<1:K> therein, inresponse to the first to L^(th) input control signals DIN<1:L>. Aconfiguration of the information storage circuit 35 will be described indetail with reference to FIG. 6.

The counter 36 may generate the first to L^(th) access informationsignals AIF(1)<1:K>˜AIF(L)<1:K> in response to the reset signal RST andthe count increment signal CNT_INC. The counter 36 may initialize thefirst to L^(th) access information signals AIF(1)<1:K>˜AIF(L)<1:K> sothat the first to L^(th) access information signalsAIF(1)<1:K>˜AIF(L)<1:K> have initial values when the reset signal RST isenabled. The counter 36 may initialize any one access informationsignal, which is selected from the first to L^(th) access informationsignals AIF(1)<1:K>˜AIF(L)<1:K> by a corresponding one of the first toL^(th) output control signals DOUT<1:L> that is enabled, in response tothe enabled reset signal RST during the first period, so that theselected access information signal has an initial value. The counter 36may count any one access information signal, which is selected from thefirst to L^(th) access information signals AIF(1)<1:K>˜AIF(L)<1:K> by acorresponding one of the first to L^(th) output control signalsDOUT<1:L> that is enabled, in response to the count increment signalCNT_INC, which is enabled during each of the second and third periods.

In this embodiment, the access information signal, which has beeninitialized or counted-up, is stored in the information storage circuit35 in response to a corresponding one of the first to L^(th) inputcontrol signals DIN<1:L>. At the same time, the access informationsignal, which has been initialized or counted-up, is also provided tothe refresh control circuit 37.

The refresh control circuit 37 may perform a refresh operation inresponse to the first to L^(th) access information signalsAIF(1)<1:K>˜AIF(L)<1:K>. The refresh control circuit 37 may perform arefresh operation for memory cells (not shown) selected by a row addresscorresponding to an access information signal, which is counted by morethan a predetermined number of times (or maximum counter value), fromamong the first to L^(th) access information signalsAIF(1)<1:K>˜AIF(L)<1:K>. That is, the refresh operation is performed onmemory cells (not shown) that are selected by a row addresscorresponding to an access information signal, which has a value greaterthan the predetermined number of times.

FIG. 6 is a block diagram illustrating the information storage circuit35 included in the semiconductor device of FIG. 5 according to anembodiment of the present disclosure. The information storage circuit 35may include first to L^(th) storage circuits 35(1)˜35(L).

The first storage circuit 35(1) may output the first access informationsignal AIF(1)<1:K> to the counter 36 in response to the first outputcontrol signal DOUT<1>, and receive the first access information signalAIF(1)<1:K> from the counter 36 in response to the first input controlsignal DIN<1>. The first storage circuit 35(1) may output the firstaccess information signal AIF(1)<1:K> stored therein when the firstoutput control signal DOUT<1> is enabled. The first storage circuit35(1) may receive and store the first access information signalAIF(1)<1:K> therein when the first input control signal DIN<1> isenabled.

The second storage circuit 35(2) may output the second accessinformation signal AIF(2)<1:K> to the counter 36 in response to thesecond output control signal DOUT<2>, and receive the second accessinformation signal AIF(2)<1:K> from the counter 36 in response to thesecond input control signal DIN<2>. The second storage circuit 35(2) mayoutput the second access information signal AIF(2)<1:K> stored thereinwhen the second output control signal DOUT<2> is enabled. The secondstorage circuit 35(2) may receive and store the second accessinformation signal AIF(2)<1:K> therein when the second input controlsignal DIN<2> is enabled.

The (N−1)^(th) storage circuit 35(N−1) may output the (N−1)^(th) accessinformation signal AIF(N−1)<1:K> to the counter 36 in response to the(N−1)^(th) output control signal DOUT<N−1>, and receive the (N−1)^(th)access information signal AIF(N−1)<1:K> from the counter 36 in responseto the (N−1)^(th) input control signal DIN<N−1>. The (N−1)^(th) storagecircuit 35(N−1) may output the (N−1)^(th) access information signalAIF(N−1)<1:K> stored therein when the (N−1)^(th) output control signalDOUT<N−1> is enabled. The (N−1)^(th) storage circuit 35(N−1) may receiveand store the (N−1)^(th) access information signal AIF(N−1)<1:K> thereinwhen the (N−1)^(th) input control signal DIN<N−1> is enabled.

The N^(th) storage circuit 35(N) may output the N^(th) accessinformation signal AIF(N)<1:K> to the counter 36 in response to theN^(th) output control signal DOUT<N>, and receive the N^(th) accessinformation signal AIF(N)<1:K> from the counter 36 in response to theN^(th) input control signal DIN<N>. The N^(th) storage circuit 35(N) mayoutput the N^(th) access information signal AIF(N)<1:K> stored thereinwhen the N^(th) output control signal DOUT<N> is enabled. The N^(th)storage circuit 35(N) may receive and store the N^(th) accessinformation signal AIF(N)<1:K> therein when the N^(th) input controlsignal DIN<N> is enabled.

The (N+1)^(th) storage circuit 35(N+1) may output the (N+1)^(th) accessinformation signal AIF(N+1)<1:K> to the counter 36 in response to the(N+1)^(th) output control signal DOUT<N+1>, and receive the (N+1)^(th)access information signal AIF(N+1)<1:K> from the counter 36 in responseto the (N+1)^(th) input control signal DIN<N+1>. The (N+1)^(th) storagecircuit 35(N+1) may output the (N+1)^(th) access information signalAIF(N+1)<1:K> stored therein when the (N+1)^(th) output control signalDOUT<N+1> is enabled. The (N+1)^(th) storage circuit 35(N+1) may receiveand store the (N+1)^(th) access information signal AIF(N+1)<1:K> thereinwhen the (N+1)^(th) input control signal DIN<N+1> is enabled.

The L^(th) storage circuit 35(L) may output the L^(th) accessinformation signal AIF(L)<1:K> to the counter 36 in response to theL^(th) output control signal DOUT<L>, and receive the L^(th) accessinformation signal AIF(L)<1:K> from the counter 36 in response to theL^(th) input control signal DIN<L>. The L^(th) storage circuit 35(L) mayoutput the L^(th) access information signal AIF(L)<1:K> stored thereinwhen the L^(th) output control signal DOUT<L> is enabled. The L^(th)storage circuit 35(L) may receive and store the L^(th) accessinformation signal AIF(L)<1:K> therein when the L^(th) input controlsignal DIN<L> is enabled.

An operation of the semiconductor device having the aforementionedconfiguration will be described hereinafter in detail with reference toFIG. 7 in conjunction with an example in which the number “J” of bitsincluded in the first to J^(th) neighboring addresses NADD<1:J> is two,and an active period T21˜T24 when an active operation is performed isdivided into a first period T21˜T22, a second period T22˜T23, and athird period T23˜T24.

During the first period T21˜T22 when the first period signal PDS1 isenabled, the N^(th) row address RADD<N> may be selected as the targetaddress TADD. The N^(th) output control signal DOUT<N>, whichcorresponds to the N^(th) row address RADD<N>, and the reset signal RSTmay be enabled to have a logic “high” level as the N^(th) row addressRADD<N> is selected as the target address TADD. The N^(th) accessinformation signal AIF(N)<1:K> may be initialized to have an initialvalue by the N^(th) output control signal DOUT<N> and the reset signalRST.

During the second period T22˜T23 when the second period signal PDS2 isenabled, the (N−1)^(th) row address RADD<N−1> may be selected as thefirst neighboring address NADD<1> when the N^(th) row address RADD<N> isselected as the target address TADD. The (N−1)^(th) output controlsignal DOUT<N−1>, which corresponds to the (N−1)^(th) row addressRADD<N−1>, and the count increment signal CNT_INC may be enabled to havea logic “high” level. As a result, the (N−1)^(th) access informationsignal AIF(N−1)<1:K> may be counted by the count increment signalCNT_INC, by increasing a value of the (N−1)^(th) access informationsignal AIF(N−1)<1:K> by an increment of one.

During the third period T23˜T24 when the third period signal PDS3 isenabled, the (N+1)^(th) row address RADD<N+1> may be selected as thesecond neighboring address NADD<2> when the N^(th) row address RADD<N>is selected as the target address TADD. The (N+1)^(th) output controlsignal DOUT<N+1>, which corresponds to the (N+1)^(th) row addressRADD<N+1>, and the count increment signal CNT_INC may be enabled to havea logic “high” level. The (N+1)^(th) access information signalAIF(N+1)<1:K> may be counted by the count increment signal CNT_INC byincreasing a value of the (N+1)^(th) access information signalAIF(N+1)<1:K> by an increment of one.

As described above, a semiconductor device according to anotherembodiment may reset a value of an access information signalcorresponding to a row address, which is selected as a target address,and may count a value of an access information signal corresponding to arow address, which is set as a neighboring address. Electric chargesstored in memory cells connected to a neighboring word line selected bythe row address set as the neighboring address may be lost due tointerference between a target word line, which is selected by the rowaddress set as the target address, and the neighboring word line, whichis selected by the row address set as the neighboring address. Thus, arefresh operation may be performed to refresh memory cells connected toa word line when the word line is selected as a neighboring word linemore than a predetermined number of times. As a result, a speed of therefresh operation may be improved and power consumption may be reducedduring the refresh operation. In addition, a counter may be shared whilethe access information signals are counted or initialized becausecounting operations for the access information signals are sequentiallyperformed in response to the first to L^(th) output control signalsDOUT<1:L>, which are selectively enabled. Accordingly, the number ofcounters may be reduced in order to decrease a layout area of thesemiconductor device.

At least one of the semiconductor devices described with reference toFIGS. 1 to 7 may be applied to an electronic system that includes amemory system, a graphic system, a computing system, a mobile system, orthe like. For example, as illustrated in FIG. 8, an electronic system1000 according an embodiment may include a data storage circuit 1001, amemory controller 1002, a buffer memory 1003, and an input/output (I/O)interface 1004.

The data storage circuit 1001 may store data transmitted from the memorycontroller 1002, or may read and output the stored data to the memorycontroller 1002, in response to a control signal generated by the memorycontroller 1002. The data storage circuit 1001 may include at least oneof the semiconductor devices illustrated in FIGS. 1 and 5. Meanwhile,the data storage circuit 1001 may further include a nonvolatile memorythat can retain stored data even when its power supply is interrupted.The nonvolatile memory may be a flash memory such as a NOR-type flashmemory or a NAND-type flash memory, a phase change random access memory(PRAM), a resistive random access memory (RRAM), a spin transfer torquerandom access memory (STTRAM), a magnetic random access memory (MRAM),or the like.

The memory controller 1002 may receive a command from an external device(e.g., a host device) through the I/O interface 1004 and may decode thecommand received from the host device to control an operation forstoring data in the data storage circuit 1001 or the buffer memory 1003,or to control an operation for outputting the data stored in the datastorage circuit 1001 or the buffer memory 1003. Although FIG. 8illustrates the memory controller 1002 with a single block, the memorycontroller 1002 may include a first controller for controlling the datastorage circuit 1001 comprised of a nonvolatile memory and a secondcontroller for controlling the buffer memory 1003 comprised of avolatile memory.

The buffer memory 1003 may temporarily store data, which are processedby the memory controller 1002. That is, the buffer memory 1003 maytemporarily store data, which are read from or to be stored in the datastorage circuit 1001. The buffer memory 1003 may store the data, whichare transmitted from the memory controller 1002, in response to acontrol signal generated by the memory controller 1002. The buffermemory 1003 may read out data from the data storage circuit 1001,temporarily store the read-out data, and output the read-out data to thememory controller 1002. The buffer memory 1003 may include a volatilememory such as a dynamic random access memory (DRAM), a mobile DRAM, astatic random access memory (SRAM), or the like.

The I/O interface 1004 may physically and electrically connect thememory controller 1002 to the external device (e.g., the host device).Thus, the memory controller 1002 may receive control signals and datasupplied by the external device (e.g., the host device) through the I/Ointerface 1004, and may output data from the memory controller 1002 tothe external device (e.g., the host device) through the I/O interface1004. That is, the electronic system 1000 may communicate with the hostdevice through the I/O interface 1004. The I/O interface 1004 mayinclude one or more of various interface protocols such as a universalserial bus (USB), a multi-media card (MMC), a peripheral componentinterconnect-express (PCI-E), a serial attached SCSI (SAS), a serial ATattachment (SATA), a parallel AT attachment (PATA), a small computersystem interface (SCSI), an enhanced small device interface (ESDI), anintegrated drive electronics (IDE), and so on.

The electronic system 1000 may be used as an auxiliary storage device ofthe host device or an external storage device. The electronic system1000 may include a solid state disk (SSD), a USB memory, a securedigital (SD) card, a mini secure digital (mSD) card, a micro securedigital (micro SD) card, a secure digital high capacity (SDHC) card, amemory stick card, a smart media (SM) card, a multi-media card (MMC), anembedded multi-media card (eMMC), a compact flash (CF) card, or thelike.

Embodiments of the present disclosure have been disclosed above forillustrative purposes. Those skilled in the art will appreciate thatvarious modifications, additions and substitutions are possible, withoutdeparting from the scope and spirit of the present disclosure asdisclosed in the accompanying claims.

1. A semiconductor device comprising: a counter control signal generation circuit configured to generate a count enablement signal, a reset signal, and a count increment signal based on a first row address selected as a target address and a second row address selected as a neighboring address of the target address; and an access information generation circuit configured to receive the count enablement signal, the reset signal, and the count increment signal and generate first and second access information signals, the first access information signal including information on the number of times that the first row address has been selected, the second access information signal including information on the number of times that the second row address has been selected.
 2. The semiconductor device of claim 1, wherein the first row address is generated by decoding an address signal, and is enabled to activate a target word line.
 3. The semiconductor device of claim 2, wherein the second row address is generated based on the first row address, and is enabled to activate a neighboring word line adjacent to the target word line.
 4. The semiconductor device of claim 1, wherein the first access information signal is initialized in response to the reset signal.
 5. The semiconductor device of claim 1, wherein the second access information signal is counted in response to the count enablement signal and the count increment signal.
 6. The semiconductor device of claim 5, wherein the count enablement signal includes a first count enablement signal and a second count enablement signal, and wherein the reset signal includes a first reset signal and a second reset signal.
 7. The semiconductor device of claim 6, wherein the first reset signal is enabled when the first row address is selected as the target address.
 8. The semiconductor device of claim 7, wherein the access information generation circuit includes a first counter that initializes the first access information signal in response to the first reset signal.
 9. The semiconductor device of claim 6, wherein the second count enablement signal is enabled when the second row address is selected as the neighboring address.
 10. The semiconductor device of claim 9, wherein the access information generation circuit includes a second counter that counts the second access information signal in response to the second count enablement signal and the count increment signal.
 11. The semiconductor device of claim 1, further comprising a target address generation circuit that decodes the address signal and generates the first row address, the first row address being selected as the target address.
 12. The semiconductor device of claim 1, further comprising a period signal generation circuit that decodes a command and generates a period signal, the period signal being enabled during a period when a predetermined internal operation is performed.
 13. The semiconductor device of claim 12, wherein the predetermined internal operation includes any of an active operation, a read operation, a write operation, and a standby operation.
 14. The semiconductor device of claim 1, further comprising a refresh control circuit configured to perform a refresh operation in response to the first and second access information signals.
 15. A semiconductor device comprising: a control signal generation circuit configured to generate, based on a first row address selected as a target address during a first period, a first output control signal, a first input control signal, and a reset signal, and to generate, based on a second row address selected as a neighboring address of the target address during a second period, a second output control signal, a second input control signal, and a count increment signal; an information storage circuit configured to store and output a first access information signal and a second access information signal in response to the first input control signal, the first output control signal, the second input control signal, and the second output control signal, the first access information signal including information on the number of times that the first row address is selected, the second access information signal including information on the number of times that the second row address is selected; and a counter configured to reset the first access information signal and count the second access information signal in response to the reset signal and the count increment signal, respectively, when the first and second output control signals are enabled.
 16. The semiconductor device of claim 15, wherein the first and second periods are set by dividing a period when a predetermined internal operation is performed.
 17. The semiconductor device of claim 15, wherein the control signal generation circuit is configured to generate the first output control signal and the reset signal, the first output control signal and the reset signal being enabled during the first period.
 18. The semiconductor device of claim 17, wherein, when the first output control signal and the reset signal are enabled, the first access information signal is inputted to the counter and the counter is initialized.
 19. The semiconductor device of claim 15, wherein the control signal generation circuit is configured to generate the second output control signal and the count increment signal, the second output control signal and the count increment signal being enabled during the second period.
 20. The semiconductor device of claim 19, wherein, when the second output control signal and the count increment signal are enabled, the second access information signal is inputted to the counter and is counted.
 21. The semiconductor device of claim 16, further comprising a period signal generation circuit configured to divide the period, in which the predetermined internal operation is performed, into the first period and the second period, and is configured to generate a first period signal, which is enabled during the first period, and a second period signal, which is enabled during the second period.
 22. The semiconductor device of claim 15, further comprising a refresh control circuit configured to perform a refresh operation in response to the first and second access information signals. 